GaAs JFETs intended for deep cryogenic VLWIR readout electronics

GaAs junction field-effect transistors (JFETs) are promising for deep cryogenic (<10K) readout electronics applications. This paper presents the structure and fabrication of GaAs JFETs and their performance at 4 K. It is shown that these JFETs operate normally at 4 K, with no anomalous behavior such as kinks or hysteresis. The noise voltage follows a 1 / f i dependence and is approximately 1 ~ V I & at 1 Hz for a ring JFET that is 1250 pm in circumference and 5 pm long. The gate leakage current reaches 1 pA at a gate voltage of -6 V. Future imaging instruments for very long wavelength infrared (VLWIR) will use detector arrays cooled to deep cryogenic temperatures (below 10 K), and will require readout electronics that operate at the detector temperature. For previous cryogenic arrays of only a few pixels, it had been possible to isolate the electronics in a warm compartment and run wires to each detector in the array. The large heat load carried by these wires, and their susceptibility to crosstalk and noise pickup makes this approach impractical for the larger formats planned for future space-based VLWIR imagers. For this reason, NASA has actively been exploring readout electronics which can be functional below 10 K. Typically, VLWIR detectors have very high impedance and low dark currents, so the readout input currents must be low. Also, the expected signals are small, requiring low amplifier noise to preserve the sensitivity. For example, the Space Infrared Telescope Facility (SIRTF) plans to use detectors cooled to 2 K that will require amplifiers with less than 10-l7 amp input current, and with a noise of less than 1 p ~ ~ & at 1 Hz. Readout electronics for the deep cryogenic temperature range is challenging for the designer of semiconductor transistors because of the phenomenon of carrier freeze-out. It takes a small but finite energy to liberate carriers from dopant atoms in lightly or moderately doped semiconductors. At sufficiently low temperature the carriers lack the thermal energy to remain free, and are recaptured by the dopant atoms. Freeze-out results in transistor performance degradation including excess noise, current-voltage anomalies such as kinks and hysteresis, or even complete device failure. For higher temperature operation, silicon-based electronics exist that are completely adequate for most read-out applications. However, silicon is not well suited to deep cryogenic operation. Moderately doped silicon freezes out above 40 K [I], causing silicon bipolar transistors and JFETs to fail by that temperature. Conventional silicon MOSFETs, which use highly doped source and drain regions, can operate down to somewhat lower temperatures by inducing an inversion charge in the frozen out channel. Below about 20 K, however, the noise becomes excessive for many applications, and kinks and hysteresis become apparent. Article published online by EDP Sciences and available at http://dx.doi.org/10.1051/jp4:1994623 C6-148 JOURNAL D E PHYSIQUE IV Therefore, a transistor technology must be developed for deep cryogenic applications. One approach is to optimize silicon MOSFET readout electronics by carehlly tailoring the doping, in order to reduce the noise and anomalies at deep cryogenic temperatures. This has been undertaken at TRW [2], and is presently underway at other silicon foundries. Another approach is to develop readout electronics in a materials system which has already demonstrated good deep cryogenic performance, such as GaAs JFETs [3,4]. GaAs JJ?ETS are well suited to deep cryogenic applications because of the very small electron effective mass in GaAs. This small mass results in the donor states being very shallow, that is, it requires a very small energy to liberate electrons from donor atoms in GaAs. Also, the small effective mass implies that the radius of the bound donor states are very large, and it requires a relatively low doping concentration before the mean distance between dopant atoms is smaller that the bound state radius. When this occurs, the semiconductor becomes degenerate, that is, the dopant atoms states merge with the free carrier bands, and the semiconductor becomes immune to freeze-out. In n-type GaAs, degeneracy occurs for doping concentrations of less than 1x1016 ~ m ~ , which is low enough to allow depletion at reasonable voltages. Holes in GaAs have a much lar er effective mass, but p-type GaAs can still be made degenerate by doping to concentrations above 5xlOlfcm-3 [I]. Thus, a GaAs JFET that is immune to freeze-out can be constructed by using a p-n junction of heavily doped p-type GaAs on top of moderately doped n-type GaAs. Such a transistor is expected to have deep cryogenic noise performance comparable to silicon devices operated above their freeze-out temperature. We have fabricated GaAs JFETs with the structure shown in Fig. 1. Starting on a semi-insulating GaAs substrate, molecular beam epitaxy (MBE) is used to epitaxially grow an undoped spacer layer, a moderately doped n-type channel layer, and a degenerately doped p-type gate layer. A tri-layer gate metal of titanium, platinum, and gold is deposited and patterned by liftoff, using image reversal photolithography. The structure is then wet chemically etched using a NH40H:H202:H20 (25:1:6250) solution with the gate metal acting as a self aligned mask. This removes the p-type GaAs everywhere except directly under the gate metal. Devices are isolated by a mesa etch protected by photoresist, and using the same etchant as the gate etch. A tri-layer ohmic contact metalization consisting of nickel, germanium, and gold is deposited and patterned by liftoff The structure is then sintered at 410 "C for 13 seconds to alloy the ohmic contacts. Lastly, an overlayer of gold is deposited on the ohmic contacts and gate metal, in order to facilitate wire bonding. Fig. 1 The structure of the GaAs JFET A set ring JFETs were measured at 300 K and 4 K. The gate formed a ring 400 pm in diameter (1250 pm in circumference) which separated the central source fiom the surrounding drain. The various JFETs had gate lengths of 5, 10, 20, and 50 pm. For this particular set of devices, the p+ gate layer was 500 nm thick and doped to greater than 5 x 1 0 1 ~ cm-3; the n-type channel layer was 375 nm thick and doped to 5 x 1 0 ~ ~ m ~ ; the buffer was 1 pm thick. The transistor curves for the 50 pm gate-length JFET are shown for the JFET at room temperature Fig. 2, and at 4 K in Fig. 3. 30 0 0 1 2 3 4 5 6 7 8 9 . 1 0 Drain-Source Voltage VDs (Volts) Ring JFET at 300 K Fig. 2: The transistor curve of a GaAs JFET at room temperature. : 1250 pm in circumference and 50 pm long and 50 . 40 v, , = 0 v